SHF: Small: Synthesis of Robust Clock Networks for Multiple-Corner Multiple-Mode Designs

Purdue University, West Lafayette IN

Investigators

Abstract

Integrated circuits for power-conscious electronics commonly found in mobile and portable devices typically operate in several operational modes in order to deliver adequate performance while maintaining energy efficiency. These circuits also have to operate robustly even under uncertainties injected by the manufacturing process and operating environments. The operation of such a complex circuit or system is synchronized by a network that delivers a clocking signal to various components of the circuit or system. Success in this research will lead to highly scalable synthesis tools that can competently design robust clock networks to synchronize large-scale high-complexity integrated circuits for mobile applications. Summer camp activities and community outreach activities that embed essential concepts related to circuits, systems and computing will be developed, benefiting K-12 students and broadening the participation of underrepresented students in computer engineering. With the integration of research results into the undergraduate and graduate curricula, students will be trained with a broad range of skills, in areas such as circuits, numerical linear algebra, and fundamental algorithms. The existing approaches of synthesizing a robust clocking system involve the application of iterations of legalization steps to correct the timing violations of an initial clock network in different operating scenarios. In contrast to such a lengthy iterative process that has no guarantee of convergence to a feasible solution, a correct-by-construction approach will be developed in this project. The proposed research activities are driven by a reconfigurable circuit structure that could robustly deliver the clocking signal for different modes of operation, while accounting for different corners of manufacturing process and operating environments. The fundamental problems of scheduling the arrival times of clocking signals at different components of a circuit under various operating scenarios will be explored. Various techniques of inserting safety margins into the reconfigurable circuit structure will be developed. For some critical components, redundant paths will be inserted such that the synchronizing signal could be delivered to them robustly should a failure occur in one of the redundant paths. A new suite of circuits for various benchmarking purposes will also be made available to promote research in this important area.