EAGER: Novel Memory Design with Ballistic Deflection Transistors

University Of Massachusetts Lowell, Lowell MA

Investigators

Abstract

Building exascale computing systems using conventional silicon technology is prohibitive due to the excessive power consumption and poor power efficiency of the system. The majority of the power consumed by a computer system is attributed to the operation of the memory. In addition, embedded memories typically occupy up to 80% of the area of the microprocessor. The realization of new technologies that offer significant (orders of magnitude) improvements in speed, power consumption, and integration densities is needed. Presently there is no clear winner for next-generation circuit technology; however, nanoscale devices and structures based on quantum transport is one of the choices. In this category, ballistic transport nanostructures operational at room temperature are gaining momentum. Ballistic Deflection Transistor (BDT) technology offers picosecond nanoscale memory design opportunities. The goal of this project is to investigate the physics and limitations of integrating picosecond BDT memories on a larger scale and the impact on fabrication, experimental characterization, and physical modeling. The project offers students working on the project interdisciplinry training in material science, device physics, nanofabrication, and advanced electronics. This project will pave the way to transformational concepts and ideas in design of ultrafast nanoscale latches and memories, enabling efforts towards exascale for nxt generation of computing capabilities. It encompasses device physics and modeling, novel architectures, and covers four focus areas and a special demonstration project: (1) Modeling of ballistic nanodevices and circuits using the ballistic mobility concept based on carrier transport in media with nonlinear conductivity, (2) Fabrication and characterization of nano-scale ballistic deflection transistors (BDTs) and their implementation as THz-switching digital circuit elements integrated into memory circuits; (3) Development of the concept of BDT access switches for memory cell control: and 4) Investigation of early concepts of Sub-picosecond (THz bandwidth) BDT RAM cell design operation based on ballistic nanodevices. The concept of a new memory cell will revolutionize data storage systems. To prove the feasibility of concept, a six terminal ballistic deflection transistor comprising a source terminal, two gate terminals and three drain terminals will be fabricated, with a triangular shape deflector in its center. The deflector will be placed in such a way that left, right and top (bottom) vertex of it is pointed towards the left drain terminal, right drain terminal and source terminal of BDT respectively. This coplanar structure will be etched into an InGaAs 2DEG. The electrons will enter the channel from the source terminal of BDT. The left and right input gates will be used to steer the electrons towards left and right drain terminals respectively. The top drain will be used to change the electron velocity. Upon collision with central deflector, electrons will gain their momentum to move quickly towards the output drain terminals. If successful, the project will revolutionize the performance and power efficiency of modern memories capable of supporting exascale for next generation computing needs.