CAREER: Energy-Efficient and Energy-Proportional Silicon-Photonic Manycore Architectures

Northwestern University, Evanston IL

Investigators

Abstract

Increasing energy demands have put computing on an unsustainable technological, economic and environmental path. Unfortunately, a large fraction of this energy is wasted, with data transfers being one of the major contributors to energy consumption. At the same time, while the demand for computing grows, modern microprocessors are increasingly constrained by physical limitations, which prevent them from realizing their full potential. Area, power, thermal, off-chip bandwidth, and yield limitations constrain single-chip designs to a relatively small number of cores, beyond which scaling becomes impractical. Multi-chip designs can overcome these limitations, but require a cross-chip interconnect with bandwidth, latency, and energy efficiency characteristics well beyond the reach of conventional electrical signaling. Introduction of nano-photonic interconnects, as undertaken in this proposal, can meet these requirements and allow systems to break free of the limitations of single-chip designs. Within the context of this research, a rigorous educational plan is also integrated into the research agenda that strongly connects research to education, and enhances the participation of minorities and undergraduates in research. This project capitalizes on existing collaborations with the Searle Center for Teaching Excellence at Northwestern University to implement innovative educational approaches, Northwestern?s Science in Society outreach initiatives for the general public, and Northwestern?s Office of STEM Education Partnerships to develop K-12 STEM outreach activities with outreach potential extending to 140+ schools in the Chicago metropolitan area, reaching 368 teachers and 30,000 students. Specific technical aspects of this research aims to develop scalable, energy-efficient, and energy-proportional interconnects for future multicores. To achieve this vision, the research seeks to understand and mitigate the energy inefficiencies of the dominant power consumers in silicon-photonics. The project involves a cross-cutting approach to combine developments in novel materials, emerging devices, and 3D-stacking with research in architectural and micro-architectural techniques, memory systems, the runtime environment, and the operating system, to develop adaptive techniques that minimize the energy consumed by nano-photonic interconnects without sacrificing their performance. The overall effort culminates on the design of a virtual macro-chip, a disaggregated many-core design supported by a silicon-photonic interconnect that reaches scales of thousands of cores, at a performance and power level impossible to realize with conventional technology.