EAGER: A Novel Approach to Application Specific Instruction Processor Synthesis from Polychronous Specifications

Virginia Polytechnic Institute And State University, Blacksburg VA

Investigators

Abstract

Complex embedded systems contain a multitude of sensors, actuators, and a number of micro-controllers or embedded processors, which require complex multi-threaded programming with synchronizations that are conditional. The task of implementing such software manually is error-prone leading to crucial errors, and hence require expensive validation. Due to inherent difficulties of post-implementation verification, this project takes the approach of synthesizing systems that are correct by construction. This project uses a polychronous data-flow specification language which lends itself naturally to multithreaded software synthesis. The theory and tools developed in this project will enable software/hardware synthesis from the same specification which could have a significant impact for a wide array of safety-critical embedded systems. This project provides a new semantics to polychronous specification languages in the form of conditional partial orders, and utilizes this semantics to develop algorithms for application specific processor synthesis. To synthesize the processor, the investigators identify the instruction sets required, and optimize their implementations, while the synthesis of the micro-code programs to implement the functionalities are derived by schedule synthesis.