SHF: Small: Variation "Immune System" for Ultra Low Power Systems-on-Chip

University Of Virginia Main Campus, Charlottesville VA

Investigators

Abstract

A wide variety of emerging applications require electronics that operate at ultra-low power levels. To achieve extreme energy efficiency, such circuits operate at low voltages where they are "off" by conventional definitions and use tiny leakage currents, analogous to dripping faucets, to do useful work. This approach promises to revolutionize design on the power side, but a critical obstacle is the heightened sensitivity of low voltage circuits to variations in the transistor fabrication process, voltage and temperature, which limit product yield. An adaptive system that adjusts chip operation to account for such variations could potentially solve this problem and provide adequate yield to deploy ultra-low power circuits in high volumes. This project's objective is to create a new paradigm for ultra-low power chips in which a variation "immune system" internally adjusts circuit level knobs to meet system level requirements across variations. The technical results from this project could improve manufacturing yield, lower costs for commercial products, and enable a swath of applications that are currently not commercially viable. While the scope of applications is in wearable computing having a broad societal appeal, the project also plans to heavily involve of female and minority students in educational outreach activities. While current efforts to build ultra-low power ICs forcibly apply the conventional fixed voltage, fixed frequency approach, this project recognizes that chips should guarantee certain system level metrics and then release constraints on parameters that are conventionally fixed, which can instead act as knobs to compensate for variations in the process technology or environment. These knobs are used in the feedback controlled "immune system" to compensate for variations. Specific research in this effort creates low overhead hardware knobs for managing variations, and co-designs software for managing chip operation in a resource constrained space. At the chip level, this approach combines variants of dynamic voltage scaling and adaptive voltage scaling methods with mode based power management control and block specific tuning to maintain proper function and meet system metrics. Additionally, the proposed scheme uses co-design of integrated components and system design to ensure robust operation despite the exponential impact of process, voltage and temperature variations at low voltage.