CSR: Small: DARP: Promoting Energy Efficient System Design Through a Dynamically Adaptable Resilient Pipeline

Utah State University, Logan UT

Investigators

Abstract

Variability of transistor behavior including delay has traditionally been mitigated through overly conservative design choices at the circuit level that come at the expense of energy efficiency. The objective of this project is to develop techniques for more effectively managing delay at the architectural level through the study of variable-delay pipelines. The long-term goal of the project is to improve the energy efficiency of computers. This project involves managing application induced pipeline delay variability, both at the core level and at the system level, outlining a transformative approach to promote sustainable computing. The project advocates cross-layer circuit-architectural design themes, which are becoming indispensable for future system designs. Various research tasks of this project explore circuit level delay variability in a pipelined microprocessor by demonstrating three intriguing axes: (a) temporal--delay variation within a given pipe stage during different phases of a program; (b) spatial--distinct delay distributions among different pipe stages of a microprocessor; and (c) workload--unique delay profiles of various pipe stages seen among various workloads. These are carefully analyzed to design a Dynamically Adaptable Resilient Pipeline (DARP), which outlines a next wave of innovation in pushing the energy efficient frontier of pipelined microprocessor design. Through educational activities with the cross-layer infrastructure, this project will be instrumental in creating a future work force well placed to exercise cross-layer themes in sustainable computer design.