SHF: Small: 100GHz DIgital Logic Using Cooled Commodity CMOS Technologies

Carnegie Mellon University, Pittsburgh PA

Investigators

Abstract

The scaling of integrated circuit process technology over the past few decades has enabled ever faster, smaller, and lower power micro-electronics. However, as process technologies near fundamental scaling limits, the pace of improvement in micro-electronics has slowed. This project seeks to boost the performance of digital integrated circuits made in current process technologies to unprecedented performance levels by cooling them to cryogenic temperatures. With this approximately order-of-magnitude performance gain, one may enable new classes of applications without needing fundamental breakthroughs in process technology. While much of the recent research in digital systems has been focused on exploiting parallelism (e.g., many-core CPUs), there remains a significant need for faster sequential processing. Even in highly parallelized systems, serial sections of code and Amdahl's Law can be bottlenecks to compute performance. Further, many users have critical, but un-modifiable, serial legacy code or applications that are inherently serial and non-parallelizable. The proposal explores extremely high clock rate digital systems in the "performance-at-all-costs" region of the design space using aggressively cooled commodity CMOS systems with a target clock rate of 100GHz, whereas the present commodity CMOS process technologies can achieve performance near 10GHz only. The project proposes to bridge this gap by building systems that use aggressive cooling, customized low-temperature circuits, and application specific architectures. Use of commodity CMOS process technologies enables both lower cost and higher integration densities than the more exotic processes, which heretofore were the only way to achieve the necessary digital logic and memory speed.