SHF: Small: Introducing Next Generation I/O Accelerator

University Of Rhode Island, Kingston RI

Investigators

Abstract

Big data applications demand high speed, reliable, and energy efficient data storage systems. Traditional storage architectures have fundamental limitations because of legacy systems that have centered on spinning hard disk drives. With rapid advances in nonvolatile memory technologies such as NAND-gate flash, phase change memory, Memristor, and magnetic RAM, a great opportunity arises for revolutionizing storage architectures. The objective of this research is to start a paradigm shift in storage architecture to meet the increasing demand of big data applications. It is envisioned that future storage systems will have machine intelligence that learns, analyzes, predicts, and controls the system at runtime dynamically. A novel accelerator architecture is introduced with machine intelligence to enable high speed processing of storage data operations that are critical to high performance computing in general and big data computing in particular. The newly introduced I/O accelerator, residing either in a many-core CPU chip or on a storage controller board, enables sufficiently accurate predictions for effective optimization of storage I/Os. With new architecture features, the proposed I/O accelerator can carry out complicated I/O tasks in the speed comparable to the emerging nonvolatile memories, which is critical to I/O performance because it no longer operates in milliseconds as spinning disks do. The project will explore and implement the I/O accelerator that can effectively deal with the complexity and high dimensionality of factors related to diverse storage technologies, a large variation of application workloads, different reliability/availability requirements, and power consumptions of various storage components. The result is a new heterogeneous storage architecture that is optimized for future computing infrastructure. With the accelerator as an enabler, comprehensive methodology will be investigated that proactively learns system behavior to anticipate long-term trends and to respond quickly to fast changing I/O events. The new architecture is believed to be the first of the kind providing dynamic optimizations by means of 1) intelligent data placements and replacements across heterogeneous devices, 2) optimal resource allocation and provisioning to applications' workloads, 3) effective data deduplication based on content locality, and 4) smart policy decision on data protection and recovery adaptive to different data types. Furthermore, the new accelerator enables fast in-situ data analytics in active storage systems. This research project is expected to have the following broader impacts: 1) In today's cloud computing and big data applications, servers generate a large amount of I/Os that can take full advantage of the new storage architecture. 2) The new accelerator can be incorporated into many core CPUs as a specialized core for future heterogeneous processors. 3) The new storage architecture will speed up the adoption of emerging storage class memories. 4) The new methodology will stimulate more research in applying machine learning to storage systems. 5) The new CPU-and-data centric Computer Engineering curriculum will train both graduate and undergraduate students for real world needs. 6) The outreach program will continue the success stories of prior NSF projects to help the economic development of the state of Rhode Island and the nation.