CAREER: Sustaining Moore's Law Through Introspective Computing: A Comprehensive System For Reliability and Energy Optimization in Modern Computing Devices

Suny At Binghamton, Binghamton NY

Investigators

Abstract

Whether one is concerned about data-center carbon footprint or battery life of mobile devices, the microprocessor is a dominating consumer of energy. Transistor technology scaling, whose rate is expressed by Moore?s Law, is a regular progression of transistor size reductions down to nanometer dimensions. Historically, this scaling has led to significant improvements in performance and energy efficiency, but more recently scaling has created severe reliability challenges due to difficulties in building components at near-atomic scale. To ensure correctness, chips are operated with static and worst-case safety margins that account for more than 70% of the total energy used by a CPU. This research program specifically addresses that energy wastage by intelligently tightening safety margins and making them dynamic in order to ensure reliable operation with dramatic reductions in expended energy. The success of this research effort will lead to substantial reduction in energy wasted by semiconductor devices for the purpose of improving battery life, environmental impact, and operating costs. It will also encourage the use of continuous self-adjustment and adaptation across an array of computing technologies. In addition to being dependent on the power supply voltage and device temperature, the power and switching delay of a transistor varies substantially with random dopant fluctuation and aging. In current practice, the worst-case combination of factors that affect transistor power consumption and delay are used to size device geometries and define an operating voltage guard band. This ensures reliable operation but leads to unnecessary energy wastage, as the worst-case combinations are unlikely to occur in reality. In this work, machine learning is used to correlate environmental and controllable factors that affect circuit delay and power and dynamically predict the minimum safe guard band. If error-resilient components are used, the guard band can be eliminated entirely. To realize maximum benefit, the system design is optimized across the boundaries of circuit, architectural, and software layers. Combining machine learning, proactive closed-loop control, and a cost/benefit-driven approach to actuator and on-chip sensor allocation, circuit designers and architects are provided with a comprehensive methodology for creating introspective computing devices that dramatically lower energy and adapt automatically to all environmental and workload conditions.