SHF:Small:Fine-Grain Many-Core Processor Arrays for Efficient Enterprise Computing

University Of California-Davis, Davis CA

Investigators

Abstract

Data centers worldwide use approximately 30 billion watts of electricity with data centers in the United States using approximately 8 to 10 billion watts. Power consumption of datacenter systems is expected to continue to grow both absolutely and as a percentage of national consumption. The goal of the proposed research is to develop massively parallel processor arrays that work in conjunction with traditional enterprise-class processors to compute datacenter workloads with vastly greater efficiency. The proposed research may lead to new applications and capabilities that were previously constrained by power dissipation or processing throughput. Project participants will propose, model, develop, and characterize novel fine-grain many-core architectures, VLSI chip designs, and application algorithms for a processor array serving as a co-processor or functional unit. The proposed programmable fine-grained many-core processor array contains no algorithm-specific hardware and is of a core granularity that is very lightly explored in prior work. The array will operate inside or near, and in co-ordination with a host enterprise-class processor and compute key computational kernels often with similar or higher performance than the host processor, but with orders of magnitude higher energy efficiency. During kernel computation, the host processor could attend to other tasks or enter a low power state. The targeted workloads include sorting, regular expression based pattern matching, encryption, data compression, video encoding and decoding, and other enterprise workloads of high impact that are discovered during the course of the research.