SHF: Small: Dynamic Power Management in the Dark Silicon Era

Cornell University, Ithaca NY

Investigators

Abstract

Future heterogeneous multicore microprocessors are expected to be so power constrained that not all transistors will be able to be powered on at once. The general-purpose cores will be required to nimbly adapt to severely constrained power allocations when power is diverted to accelerators, and vice versa. In addition, energy-aware scheduling of threads to cores is becoming imperative as multicore architectures become more heterogeneous. This research develops power gated multicore architectures and integrated scheduling and power allocation algorithms for maximizing throughput given varying and potentially stringent limits on allocated power. One facet of the research is the design, synthesis, and evaluation of power gated general-purpose and data-parallel accelerator microarchitectures comprised of deconfigurable lanes--horizontal slices through the pipeline--that permit dynamic tailoring of each core to the application. The goal is to demonstrate tolerable performance and power-gating overheads yet flexibility in adapting to workload behaviors. A second aspect of the work is a new optimization approach that efficiently finds a near-global-optimum configuration of lanes and thread-to-core assignment without requiring offline training or foreknowledge of the workload. The approach combines reduced sampling techniques, adaptation of response surface models to online optimization, incorporation of limited online profiling information, and heuristic online search. The research will improve the computational capability of future severely power-constrained devices; involve undergraduate, graduate, and/or postdoc women engineers; and be incorporated into computer architecture and heuristic optimization classes.