SHF: Small: Novel Techniques for Handling Memory Model Bugs

University Of Texas At San Antonio, San Antonio TX

Investigators

Abstract

With the ubiquitous availability of parallel architectures, the burden falls on programmers' shoulders to write correct parallel programs that have high performance and portability across different platforms. Unfortunately, most programmers find it a challenging task. One of the major issues that contribute to this challenge is the intricacies involved with the underlying memory consistency models that define the order of memory operations. The situation is worsened by the fact that the memory model specifications provided by public architecture vendors are often ambiguous, difficult to use, and even incorrect. This project looks at techniques to characterize, detect and avoid bugs caused by memory models. A memory model forms the fundamental basis for writing parallel programs. If a programmer is not careful about the constraints of the underlying memory model, a parallel program might end up having subtle bugs. In one scenario, the bugs might cause a program execution to have unintuitive interleaving of instructions, which eventually leads to incorrect behavior and lack of portability. In other scenarios, the bugs might cause a significant slowdown and poor scalability of the program. Unfortunately these bugs, referred to as Memory Model Bugs, receive very little attention from the research community. Therefore, this work focuses on developing new techniques to deal with these bugs. The work will first characterize different memory model bugs in real world code bases. The findings will be useful in developing hardware and compiler techniques (e.g., new hardware modules, exceptions, static analyzers, etc.) to detect as well as avoid these bugs. Finally, the work will focus on designing new software debugging tools to help programmers get rid of these subtle bugs. The research in this proposal will enable the widespread practice of parallel programming by addressing some of the hardest concurrency bugs. On one hand, it will encourage software and hardware companies to invest in new techniques for debugging and avoiding these bugs. On the other hand, it will help make C++ and Java memory models simple and robust.