SHF: Small: Compiling Custom Hardware Accelerators from Graph Algorithms

Carnegie Mellon University, Pittsburgh PA

Investigators

Abstract

Many emerging applications in machine learning and data mining can be cast as graph computations. Efficient low-power implementations of graph computations promise disruptive capabilities for the increasingly ubiquitous embedded and mobile platforms. The project is building the GraphGen compiler to overcome the complexity and difficulty of creating graph computation hardware accelerators that are needed to meet the demanding power and performance constraints of embedded and mobile systems. The GraphGen compiler is a general-purpose compiler (within the graph computation domain) to handle arbitrary graph applications based on varying graph structures (e.g., grid-shaped, planar, natural graphs) that may be static or dynamically changing (e.g., updated by streaming data) following different execution strategies (e.g., synchronous vs. asynchronous). GraphGen implementation mapping makes use of reusable hardware implementation templates to allow the same graph computation specification to be efficiently mapped onto different target platforms. Overall, the GraphGen compiler captures knowledge from both application developers (in graph specifications) and hardware designers (in the reusable implementation templates), and bridges the gap between the two camps through automatic mapping of a specification to a template to yield a highly efficient embedded implementation tuned to the application developer's design objectives. The continued exponential increase in transistors-per-die, coupled with advances in sensors and breakthrough algorithms in machine learning and data mining, have resulted in a revolution in the embedded and mobile application space. Graph computation is an important enabling computation paradigm for many of these emerging applications. The GraphGen compiler can facilitate rapid adoption of these applications into embedded and mobile devices by allowing domain experts to automatically translate their graph computation algorithms onto efficient FPGA-accelerated embedded platforms. This new capability has the potential to spark new research in graph computation and embedded hardware architectures by providing a common design automation environment that bridges the gap between application domain experts and hardware designers, thus benefiting industry.