Thermal-Sensitive System-Level Reliability Analysis and Management for Multi-Core and 3D Microprocessors

University Of California-Riverside, Riverside CA

Investigators

Abstract

Reliability has become a significant challenge for the current multi-core and emerging 3D microprocessor design. Many long-term failure mechanisms such as electromigration, stress migration, and thermal-cycling are very sensitive to temperature or to temperature changes. As a result, there is an urgent need for reliability awareness and optimization at the micro-architectural design stage. Since temperature has exponential impacts on many failure issues, it is crucial to have accurate and fast thermal estimation for reliability analysis and even optimization at the architecture and package levels. In this project, the principle investigator (PI) first plans to develop architecture-level full-chip reliability modeling and analysis techniques considering new structures of integration techniques and dominant hard failure mechanisms. Then the PI will develop reliability-aware dynamic thermal management techniques for multi-core and 3D stacking microprocessors. Finally, the PI will develop full-chip thermal estimation and prediction techniques considering realistic conditions such as limited physical thermal sensors and presence of errors in thermal and power models, for run time system-level reliability analysis and optimization. The outcome of this research will add significantly to the core knowledge of system-level reliability optimization techniques, which will enable more efficient thermal optimization and design of multi-core and 3D microprocessors. The interdisciplinary nature of the project will enable undergraduate and graduate students to acquire unique skills valuable to their future endeavors in STEM fields. This grant will enable the PI to hire more female and underrepresented minority students to further contribute to diversity in the science and technology workforce.