CSR: Small: Simulation of Multicore Processors with One (or More) Fast Core(s) Using Wind River SIMICS

Rensselaer Polytechnic Institute, Troy NY

Investigators

Abstract

The most important task for scientific computing is to plan the way forward from the current era of multicore microprocessors implemented in deeply submicron CMOS. This has to be done in such a way that performance improvements are guaranteed. Otherwise the escalating costs of fabrication at the nanometer scale will not be sustainable. Heterogeneous multiple core microprocessors face several major problems, not the least of which is codified in Amdahl?s Law, which shows that even relatively small amounts of serial or low-parallelism code can limit the gains that are possible. It is clear that the ultimate way to circumvent this dilemma is to greatly accelerate the serial code using a high clock rate unit (HCRU) core using a ?beyond-CMOS? device approach. Past research suggests that clock rates of 20-30 GHz are possible for many key components using BiCMOS, but 3D technology is needed to mitigate memory wall problems. This research explores a brand new 90nm IBM SiGe HBT (300GHz fT) BiCMOS process to accomplish this goal while trading excess speed for 4X lower power. The strategy will be to redesign certain critical components of a computer in this new process to verify that the same high speed is obtained at a lower power. The second thrust of the project is to verify by high-level simulation that the execution of serial code at a high clock rate will in fact result in the expected improvement in performance. This is to be conducted using the Wind River SIMICS simulation package.