SHF: Small: Enabling Techniques for Asynchronizing Synchronous Design

Iowa State University, Ames IA

Investigators

Abstract

Objective of this research is to develop an easy to apply and high quality asynchronous design flow for modern VLSI chips based on the NULL Convention Logic (NCL) asynchronization approach with proper Computer Aided Design tool support. The design flow will focus on simultaneously optimizing power, performance and area of the circuit at the logic, circuit and layout levels. New optimization techniques targeting asynchronous design will be derived and implemented into the tools. The proposed work will address an important aspect (power) in attempts to overcome Moore's law slowdown in semiconductor circuit design, manufacturing with potentially large impact to industry. The results will be integrated into graduate courses and/or senior electives in university curricula. The proposal is from an EPSCoR state, and PI will in addition recruit students from the University of Puerto Rico, which is yet another EPSCoR state. The tools developed as part of this project will be made available in the public domain. The PI has a very strong past record of developing CAD tools and making them available to the community. Overall the project exemplifies NSF commitment to the integration of research and education.