An Assessment of Options for Post-CMOS Emerging Research Devices and Related Materials: Four Workshops to be Held in 2012 in the Netherlands, Canada, France and San Francisco.

Semiconductor Research Corporation, Durham NC

Investigators

Abstract

Objective The objective of this project is to conduct an international series of four face-to-face workshops to assess quantitatively the potential and status of four topics related to research on nanoelectronics devices and materials. The topics are: Emerging Research Memory Devices, Emerging Research Logic Devices, Emerging Research Architectures, and Emerging Research Materials critical for the realization of specific nanoelectronics devices. Participants and contributors to these workshops will include academic and industrial domain experts. The outputs of these workshops will guide and input preparation of the 2013 International Technology Roadmap for Semiconductors chapters on Emerging Research Devices and Emerging Research Materials. This grant will be used to pay partial travel expenses for some presenters, particularly academics, requesting travel assistance. The workshops series will focus on the relationship between the Semiconductor Industry as it endeavors to continue to advance semiconductor technology and the work of the National Nanotechnology Initiative (NNI) research community. One purpose of these meetings is to evaluate the potential and status of each specific nanotechnology entry identified by the ITRS ERD/ERM Working Groups as having potential to enable a new paradigm for information processing. Another purpose is to identify research opportunities that, if addressed, will benefit the Semiconductor Industry and fall within the scope of the NNI research agenda. Presenters will be provided with a list of questions that are intended to stimulate discussions during the workshops. Each workshop will be documented by a report described below. Intellectual Merit In bringing together leading academic and industrial scientists to discuss, debate and reach consensus on the potential performance and key scientific challenges related to several emerging research memory and logic device technologies, these workshops will provide an excellent forum for intellectual pursuit and discernment of important/limiting scientific issues related to approaches to information processing. The intellectual merit of these workshops is illustrated by way of example. In the first example, the physics of operation and extreme scaling projections are not well understood for ?select devices? required for use in nanoscale memory arrays. These select devices are needed to employ a new class of non-volatile memory cells, called resistive random access memory (ReRAM),that may replace NAND flash for technology generations beyond the 16nm technology node. Generally speaking, a memory cell in an array can be viewed as being composed of two fundamental components: a ?storage node?, which is usually characterized by the physics of operation of the particular memory device used, and a ?selector?. The selector is a device which allows a given memory cell in an array to be singularly addressed for read or write operation without addressing its nearest neighbor cells. It is a non-linear element, which can operate as a switch, such as a diode-type, or as a resistive-switch-type structure. The latter category includes novel concepts such as Mott switches, threshold switches, and mixed ionic electronic conduction switches. Understanding the dominant physics related to their non-linear I-V characteristics is essential to employing these select devices in a highly dense non-volatile ReRAM crossbar architecture. It should be noted that for several advanced concepts of ReRAM, the storage node in principle can be scaled down below 10 nm, and the memory density will be limited by a somewhat larger conventional three-terminal select device. Thus the select device represents a serious bottleneck for scaling a ReRAM memory cell to 16 nm and beyond. Application of these new non-volatile memory devices to a crossbar memory structure will enable a paradigm shift to a new storage class memory (SCM) off-chip memory architecture discussed below. Another example, related to logic, is a family of new nanoelectronic low subthreshold-swing devices: e.g., negative Cg devices. These devices offer the attractive possibility of performing high speed logic while dissipating much lower power compared to a conventional MOSFET. The circuit design and the academic research communities have a expressed a strong interest for the ERD Technical Working Group to explore the physics of operation of these devices and the circuit design space in which they can operate in order to better understand their potential performance. This information will provide important input to these communities regarding their accelerating development of low-power electronics. Broader Impact By carefully assessing the potential performance and scientific/technological challenges for each new memory select device and of new low-power logic devices, as well as emerging architectures, these workshops will provide important documented inputs to the research community as they pursue their exploration of many emerging research devices. One venue being initiated to obtain broad dissemination of this information is the editing and publication of a comprehensive book on nanoelectronics entitled ?Emerging Nanoelectronic Devices?. A proposal is under review by a major publisher who has expressed considerable interest. Furthermore, the educational value and planning impact of these workshops on the international research community are quite substantial. Several universities (e.g., Stanford, U. Minnesota, U. Tokyo,?) use the ITRS chapters on Emerging Research Devices and Emerging Research Materials resulting from these workshops as texts in their Nanoelectronics courses. Also several international research funding agencies (e.g., SRC, NSF, and NIST Nanoelectronics Research Initiative, the EU Framework Program 8, ?) use the material in these chapters as inputs to their decisions on research directions in their Nanoelectronics research programs.