SHF:Small:Designing Low-Latency and Robust Interconnection Networks with Fine-Grain Dynamic Adaptivity Using Asynchronous Techniques

Columbia University, New York NY

Investigators

Abstract

The organization of complex heterogeneous digital systems looms as one of the fundamental research problems of the next decade and beyond. One recent promising strategy is the use of structured communication, in the form of interconnection networks or networks-on-chip (NoCs). Such NoCs have been recently used in many systems, ranging from embedded systems-on-chip for consumer applications to memory interfaces for high-end parallel processors. A number of advances have been made in the design and capabilities of synchronous (i.e. clocked) NoCs, but the increased need to support design reuse, mixed clock domains, and dynamic voltage and frequency scaling (DVFS, to improve system power), have highlighted the inherent rigidity of a single-clock framework. While a number of asynchronous and globally-asynchronous locally-synchronous (GALS) NoCs have been developed, and demonstrated benefits in some cost metrics, most have major performance and area overheads and are not competitive for a range of critical applications, while others aiming at high performance require the use of advanced circuit techniques. This proposal aims to bridge the gap, developing medium- to high-end asynchronous/GALS NoCs, using mostly standard hardware components, with significantly improved cost metrics over comparable single-clock designs: dynamic power, system latency, throughput, area and reliability. A novelty of the approach will be to explore the use of fine-grain dynamic adaptivity, at the individual router node level, where, opportunistically, nodes can reconfigure themselves to ``scavenge'' improvements in latency, throughput and static power, based on observed ambient traffic. A direct comparison will be made with state-of-the-art clocked systems, using a promising multi-synchronous approach (with a single clock rate, but tolerating phase misalignment, called ``mesochronous''). Detailed simulation and synthesis tools and support flows will also be developed. The broader impact of the proposed framework will be to provide a new level of advancement for the competitive viability of asynchronous design in overcoming key system bottlenecks. It is anticipated that this work will play a role in advancing a paradigm shift in organizing complex systems, through use of asynchrony. The results are also expected to provide a major advance in designing next-generation NoCs.