SHF: Small: Efficient Test and Yield Enhancement Techniques for 3D Integrated Circuits

University Of Texas At Austin, Austin TX

Investigators

Abstract

Three-dimensional integrated circuits (3D-ICs) using through-silicon vias (TSVs) is an important new technology that overcomes barriers in interconnect scaling. It provides significant advantages including increased functional density, higher performance, and lower power. This research project will explore new ideas, concepts, and directions for test and repair of 3D-ICs which hold promise to significantly reduce test costs and improve yield. The ability to select which dies/wafers are stacked together and in what order and with what rotational symmetry are degrees of freedom in constructing 3D-ICs that can be exploited. New strategies for using this to reduce the cost and increase the effectiveness of defect tolerance techniques will be investigated. To reduce test costs, new distributed test compression architectures will be developed which create a new paradigm for test scheduling enabling much greater flexibility and efficiency to shorten test time and improve product quality. This research project will generate new theory, concepts, and techniques for significantly improving test costs and yield for 3D-ICs. This is a key factor for keeping down the manufacturing costs of 3D chips and allowing them to penetrate new markets and benefit society. Knowledge and experience generated from this project will be incorporated into courses in VLSI design and test. Students will be trained and prepared for the next generation semiconductor workforce. Undergraduate students will be involved in the project, including those from underrepresented groups, through undergraduate research projects, senior design projects, and course projects based on this research.