EAGER: Collaborative Research: Heterogeneous Cores, Memory-Hierarchy and Communication Architectures for Future CMPs

Carnegie Mellon University, Pittsburgh PA

Investigators

Abstract

Computing has enabled immense innovations in many fields and social life due to continued performance, power, and cost improvements enabled by technology scaling. Unfortunately, two key trends threaten performance and cost improvement of computers going into the future. First, technology scaling is at jeopardy, leading to major challenges in power consumption, reliability, and performance. Second, power and energy consumption has become a key constraint, yet existing systems are mostly designed in a one-size-fits-all way agnostic to the needs of different applications. To overcome both problems, this research investigates novel uses of heterogeneous technologies in three key components of a computing system: cores, interconnect, and memory. The approach taken is an application-driven approach that aims to seamlessly integrate heterogeneity in the three components. Major expected contributions of the research include: (1) an initial study of first-principles based and application-driven design of cores, (2) new mechanisms for enabling phase-change memory based heterogeneous main memory, (3) exploration of tradeoffs in the design of 3-dimensional optical interconnects, (4) initial exploration of the interaction of heterogeneous components in cores, interconnect, and memory. The proposed research has the potential to transform the design and architecture of future multi-core systems, which are already a part of the entire IT sector and our daily lives. It can enable overcoming key challenges that impediment higher-performance and lower-power lower-cost computing, which has traditionally enabled new applications and discoveries. Enabling fundamentally efficient heterogeneous multi-core systems can largely reduce energy and technology-scaling costs of computing, and improve dependability and performance. Direct transfer of many ideas to industry are expected through extensive collaborations with platform and chip design industries.