EAGER: SHF: Harnessing Cross-Layer Heterogeneity for Future CMPs

Pennsylvania State Univ University Park, University Park PA

Investigators

Abstract

Heterogeneous multicores/Chip Multiprocessors (CMPs) are envisioned to be a key design paradigm to combat the challenges of power, memory, and reliability walls that are impeding chip design using deep sub-micron technology. There are so many dimensions to creating heterogeneous architectures, with the issues spanning multiple devices, technology platforms and software stacks. Further, despite the promise that heterogeneity offers, it is not clear (I) what are the most salient forms of heterogeneity that will be really needed, and (ii) how do all these forms interacting in non-intuitive ways at the entire system level. These issues make this topic a high-risk high-reward proposition. This project will provide preliminary results to gauge the potential and feasibility of heterogeneous architectures, and develop strategies for systematically evaluating them. The semiconductor industry is vital to the national security and economy of the United States. With all major chip vendors projecting increased number of cores as the key to their future road maps, innovations in chip multiprocessors is critical. Enabling heterogeneous computing can largely reduce energy costs of computing, while making it more powerful and dependable. Collaboration with industry partners would facilitate direct transfer of many ideas to industry. The tools and techniques developed in this research will be made publicly available.