SHF: Small: Software and Hardware Integration with Feedback and Transparency for Many-Core Computing

George Washington University, Washington DC

Investigators

Abstract

Multi-core processors are becoming prevalent and provide means for continuing to increase our computational capacity. These emerging platforms with multiple processing cores on chip offer the capability to run multiple programs simultaneously, thereby increasing the processing power of computing systems. However, since the running programs often share multi-core resources, execution interference effects between such programs can hurt their performance. Often times, software obliviousness to this underlying hardware behavior exacerbate the multi-core performance problem. Such adverse effects limit our computational progress in areas where interference can be detrimental such as high-performance computing and cloud computing, and could further complicate the predictability and deployment of these advanced processors in mission-critical domains such as avionics and automobiles. Therefore, understanding software behavior and Interference effects on multi-core processors is crucial to harnessing their full potential. In this research the investigators do preliminary studies of the issues arising from execution interference between multiple software threads on multi-core processor platforms. This research involves revisiting how hardware resource management can account for application-level constraints (such as performance isolation, fairness, and priority) by enhancing the interface between hardware and the Operating System (OS), and studying the hardware and software overheads. This research lays the groundwork for the hardware-OS interaction based on active fine-grained monitoring of resources and a two-way adaptation between both the hardware and OS to tightly control the effects of interference between threads.