II-NEW: Acquisition of Test and Measurement Equipment Enabling Design of Wireless Networks-On-Chip for Multi-Core Systems

Washington State University, Pullman WA

Investigators

Abstract

The Network-on-chip (NoC) paradigm has emerged as a scalable interconnection infrastructure for modern multi-core chips. However, with growing levels of integration traditional NoCs suffer from high latency and energy dissipation in on-chip data transfer due to conventional metal/dielectric based interconnects. The wireless NoC (WiNoC) simultaneously addresses the latency, power consumption and interconnect routing problems of conventional NoCs by replacing multi-hop wired links with high-bandwidth single-hop long-range wireless channels. Recent investigations have characterized silicon integrated on-chip antennas operating in the millimeter (mm)-wave range of 50-110 GHz, and this is now a viable technology. Coupled with significant advances in mm-wave transceiver design, this development opens up new research opportunities for WiNoCs. Successful execution of WiNoC research is possible if simulation-based feasibility studies are combined with suitable prototype development. For accurate performance evaluation and characterization of mm-wave transceiver circuits and on-chip antennas, high frequency network and spectrum analyzers, signal generators, a bit error rate tester and mm-wave on-wafer probe stations are required. To complement these research efforts, the acquired equipment will be integrated into a laboratory to support undergraduate and graduate courses in multi-core architectures, mm-wave circuits and communication systems at the Washington State University and the University of Idaho. These courses will provide students with essential hands-on training with industrial grade test and measurement tools. Eventually, this training will produce a cadre of well-trained B.S., M.S. and Ph.D. graduates who will benefit both industry and academia.