CAREER: Design Automation and Circuits for Energy Efficient Computing using Resonant Clocking

University Of California-Santa Cruz, Santa Cruz CA

Investigators

Abstract

This CAREER proposal aims to improve the energy efficiency of computer chips by developing circuits and automated design tools to recycle the energy in the power-hungry clock network that synchronizes events on most computer chips. Much like a hybrid car stores the kinetic energy during breaking into a battery for later use, the proposed resonant clocking stores the energy of the largest on-chip signal into on-chip inductors for later use. The proposed techniques combine knowledge from digital, analog, and radio-frequency (RF) circuit design and will integrate with existing low-power digital design methods and be manufactured using existing semiconductor processes. In addition to the circuits, the PI also proposes tools and design methods that will enable digital chip designers to easily include the proposed circuits by abstracting the previous broad knowledge base. This will accelerate the adoption of the proposed techniques for maximum pervasiveness and impact. The broader impact of the proposed research will be to increase power efficiency in computer chips and enable designers to include resonant clocks in chips ranging from mobile phones to large commercial servers. The previously unattainable power gains can then be used to improve battery lifetimes in mobile systems, decrease operational costs in commercial data centers, provide green computing by lessening the energy burden on our environment and improve computing performance which will enable new applications of computer systems. The PI will also pursue several educational and outreach efforts that focus on under-represented and under-privileged students in the local community through a series of seminars and summer internships.