COLLABORATIVE RESEARCH: MOSFETS WITH ATOMICALLY ENGINEERED METAL/HIGH-K INTERFACES

Rensselaer Polytechnic Institute, Troy NY

Investigators

Abstract

Field-effect Transistors with Atomically Engineered Metal/High-k Interfaces PIs: Ramprasad (U Conn, CT) and Ramanath (RPI, NY) The objective of this research is the atomic-level design of interfaces between metals and high dielectric constant insulators (high-k), with control over the metal effective work function. The approach involves the rational placement of atomic or molecular nanolayers at the interface. Density functional theory computations, synthesis strategies pioneered by us, device fabrication and characterization, will be employed to study the effects of the nanolayers on the electronic structure, bonding, and stability of metal/high-k interfaces. Intellectual Merit: For almost four decades, electronic devices have comprised of doped-polysilicon electrode/silica stacks. The inadequacy of this architecture for next-generation devices has made the development of metal electrode/high-k stacks inevitable. A critical roadblock in the latter approach is the unavailability of a clear pathway and knowledgebase for creating metal electrodes with tunable work function. This challenge will be addressed by identifying the influence of the physical and chemical features of interfacial nanolayers on the effective metal work function. Interfacial molecular nanolayers provide a completely new transformative pathway to tailor interface electronic properties and stability. Broader Impact: This project will provide a unique opportunity for cross-disciplinary training of two graduate students working on computations and experiments at University of Connecticut and Rensselaer, respectively. Integration of this research in device and materials courses at the two universities, and the computation-experiment synergy on a topic straddling nanoscience and electrical engineering will enrich the students. Site-visits for K-12 students, and a summer internship for a high-school teacher to increase their awareness on emerging nanoelectronic device architectures will be organized.