EAGER: The Exploration of Memory Hierarchy Design and Optimization for Multi-core Systems

Wright State University, Dayton OH

Investigators

Abstract

Recently, there has been a growing disparity between processor and memory speeds; this disparity is called the ?memory wall? problem. Memory performance has a dominating effect on overall system performance, especially for the data-dominated applications. Also, memory usually occupies half of the surface of the integrated chip of the multi-core system; the total amount of memory required is also a main contributor of the manufacturing cost and the chip size of the multi-core CPU. Memory also dictates the power consumption, since memories and buses consume large quantities of energy. The ?memory wall? problem becomes even more serious when throughput in the processor part is propelled by multi-core architectures. In this proposal, the PI is carrying out research to address the ?memory wall? problem and to develop potentially transformative approaches for memory hierarchy design and configuration in multi-core systems. Different memory architectures can lead to different solutions with different costs and with different performances. Memory size, memory configuration, and memory architecture will be optimized simultaneously for multi-core architectures in order to effectively and efficiently achieve higher performance.