CSR: Small: Breaking the Address Translation Barrier in Large Memory Systems

William Marsh Rice University, Houston TX

Investigators

Abstract

Today, inexpensive computer systems based on commodity, off-the-shelf components can support hundreds of gigabytes of memory. Traditionally, the demand for large-memory systems came predominantly from the operators of databases for applications such as high-volume transaction processing. Today, however, a much wider variety of applications drive the demand for such large-memory systems, ranging from server consolidation using virtualization to infrastructure for Web 2.0 applications. At a scale of 100GB or more, for many of these applications, virtual memory access becomes a bottleneck. Specifically, the overhead of address translation increases dramatically. Large pages can mitigate this problem by significantly increasing translation look-aside buffer (TLB) coverage. However, all too often these applications exhibit poor temporal and/or spatial locality of reference. Thus, even with large pages, the TLB hit rate is very low. This research will develop novel architectural mechanisms and operating systems support to mitigate the cost of address translation. Effective approaches to this problem include caching internal levels of the page table in dedicated hardware, providing hardware support to exploit physically contiguous memory reservations within the operating system, and re-examining page table organizations for large address spaces. This research will explore all of these techniques and carefully consider the interactions between memory allocation and management in the operating system and address translation overhead in the hardware. This research will transform the way in which address translation is performed on future systems, enabling the effective use of hundreds of gigabytes of memory. Currently, large memory machines suffer from address translation bottlenecks, limiting overall performance. As these machines consume significant amounts of power, this leads to poor power efficiency, wasting both energy and money. More efficient address translation will lead to significant improvements, especially in datacenters with numerous large memory machines.