SHF: CSR: Small: Assisted Partitioning and Automated Synthesis of Hybrid Manycore Simulators

Brigham Young University, Provo UT

Investigators

Abstract

Microprocessor designers wish to predict the performance of future microprocessors, evaluate new ideas, and validate new systems. The primary technique they use is software-based simulation. Unfortunately, software-based simulators for manycore microprocessors are slow and will become even slower as the number of cores increases. Slow simulators imply that little exploration of the design space can be done -- few design alternatives are considered and those that are considered are not evaluated thoroughly. Hybrid simulators, which use reconfigurable hardware devices such as Field Programmable Gate Arrays (FPGAs), could accelerate simulators by orders of magnitude, but are themselves very difficult and time-consuming to create; this difficulty arises from the need to first partition the simulator between hardware and software and then design the hardware portions. The goal of this project is to provide tools which allow a designer to easily and quickly create a hybrid simulator from a software-based simulator. The tools will assist the designer to partition the design and then automatically synthesize the hardware portions based upon the selected partitioning. Three different software simulation frameworks -- SystemC, Unisim, and the Liberty Simulation Environment -- will be supported. We target a 100x simulation speed improvement relative to software-based simulators. Achieving this target will require the development of new means to exploit parallel communication and execution between the hardware and software and new means to virtualize the hardware resources. The resulting tools will enable researchers and practitioners to better explore the manycore design space, evaluate new ideas, and validate designs.