SHF: Small: Confidence in Manycore/Multi-Core Modeling and Simulation

Georgia Tech Research Corporation, Atlanta GA

Investigators

Abstract

Computer designers use techniques to accelerate the simulation of their new computer designs while ignoring the errors of the acceleration methods. This is common because the entire simulation of modern computer programs is intractable. Basing the performance of a design only on fragments of program execution can yield results that are misleading, and result in far from optimal computer hardware designs. Without bounds on confidence, the relative performance of two architectures is impossible to compare with any statistical validity. For computer design to advance to an engineering science with reproducible results, the status quo must change. This research remedies the situation by introducing confidence bounding to fast manycore simulation. The Georgia Tech research team has made significant and lasting contributions to adding confidence to single-threaded processor simulation, and is adapting and discovering new techniques for the manycore simulation. The team is investigating several approaches to thread slip problem (where the relative execution order of threads is unknown at the start of the simulation of a cluster of events) and are developing models that can be used by designers. Another class of problems is state reconstruction problems unique to manycore simulation. For example, global ordering of thread executions and their sharing patterns greatly impact the coherence state of cache blocks. Coherence information, in addition to directory contents, indicate the current owner of a line, which must be reconstructed for measured cache latencies and interconnect network flow to be representative of unsampled execution. Other specific problems involve recovering the directory state, the state of the interconnection network (e.g., flit buffers, conflicts for routes, etc), and cache state.