EAGER: A 32 GHz RISC Computer using 3D and SiGe Emerging Technology

Rensselaer Polytechnic Institute, Troy NY

Investigators

Abstract

The most important task for scientific computing is to plan the way forward from the current era of multicore microprocessors implemented in deeply submicron CMOS. This has to be done in such a way that performance improvements are guaranteed. Otherwise the escalating costs of fabrication at the nanometer scale will not be sustainable. Multiple core microprocessors face several major problems, not the least of which is codified in Amdahl?s Law. This law states that even if multiple core processors can reduce all parallelizable code to vanishingly small run time, what will remain is serial code. Even relatively small amounts of serial code then limit the gains possible. Consequently it is prudent to pursue a balanced technology approach, in which both parallelizable and serial codes enjoy advantages. For serial code, assuming all instruction level parallelism (ILP) is fully exploited, the only way forward is to execute the serial code on a higher clock rate unit, or HCRU. Since clock rates for CMOS have tended to saturate due to wire scaling problems and excessive heat dissipation, one must look to an alternate three terminal device, but which is compatible with CMOS. This project explores whether the solution lies with an overlooked device, an aggressively scaled SiGe Heterojunction Bipolar Transistor (HBT). The claim for the research to verify is that clock rates of 20-30 GHz are possible at reasonable power levels and densities, but 3D technology is needed to mitigate memory wall problems.