Physical Modeling of Low-K Dielectric Breakdown and the Estimation of Full Chip Lifetime

Georgia Tech Research Corporation, Atlanta GA

Investigators

Abstract

"This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5)" State-of-the-art chips use low-k materials to form the insulator between interconnect lines. The use of low-k materials reduces capacitance, which in turn reduces the propagation delay between the transistor gates in a chip. To reduce delay, each technology generation involves low-k materials with progressively lower k values. These materials are formed by adding porosity and have progressively degraded reliability characteristics. Understanding the reliability of chips built with low-k materials is complicated, because reliability is a function of the complete interconnect system, including the low-k material, the cap layer, and the barrier. Hence, the materials cannot be studied in isolation, and the interfaces among the materials play a major role in breakdown. This research is developing a comprehensive understanding of breakdown of porous low-k dielectrics through the development of simulation models of breakdown and their calibration to empirical data. Backend dielectric breakdown is complicated because of the role of interfaces and the large number of defects and material irregularities in porous low-k materials. This work studies dielectric breakdown at the microscopic level, in porous materials and at interfaces (cap layer and barrier), and builds models of conduction through materials and at interfaces under stress. Empirical calibration of models involves new approaches to eliminate the impact of within and between structure linewidth variation and of field enhancement at test structure tips. The models are used to build a tool to analyze a full chip layout?s vulnerability to backend dielectric breakdown. The resulting tool should significantly reduce manufacturing risk and design respins.