CAREER: Communication-Centric Chip Multiprocessor Design

Texas A&M Engineering Experiment Station, College Station TX

Investigators

Abstract

The ever-shrinking feature size in CMOS process technology has enabled the integration of a large number of devices such as cores, caches, and other special engines in a single chip. The growing popularity of Chip Multiprocessors (CMPs) has ushered in the arrival of a communication-centric system where the design of interconnection architecture has a significant impact on the overall system performance as well as power dissipation and area of a chip. To overcome traditional interconnects problems, Network-on-chip (NoC), using switch-based networks, has been widely accepted as a promising architecture to orchestrate chip-wide communication. Although there has been significant research on NoC designs, there is still a lack of a unified design methodology integrating system and NoC design. The investigator is developing a comprehensive design paradigm for exploring the on-chip interconnect design space, especially focusing on how it interacts with the rest of the CMP architecture. This research program is comprised of four intertwined research objectives. First, simulation testbeds and traffic analysis methodologies are developed to understand the interplay between applications and system architecture. Traffic analysis tools are used to capture the runtime behavior of various applications in CMPs. Second, solutions for high and predictable performance within power and area budgets in current and future technology generations are provided. Third, the PI is developing a domain specific NoC design for CMP memory systems. As the last objective, the PI explores new opportunities and challenges posed by future applications of next-generation CMP. The research is integrated into the education curriculum, through existing and new graduate courses, and in undergraduate research programs.