CPA-CPL: Compiler and Software Solutions for the Memory Bottleneck on Multicore

Purdue University, West Lafayette IN

Investigators

Abstract

Virtually every high-performance processor today has multiple processing units (also known as cores) on a single chip. Such multicore hardware designs present opportunities for significant performance gains, by processing multiple tasks simultaneously, thus enabling novel compute-intensive applications. Executing multiple tasks on a single chip requires data to be transported in and out of the chip at a rate which often exceeds current hardware capability. Consequently, realizing the performance potential of current multicore processors requires novel solutions to the memory bottleneck problem. This project investigates software solutions to alleviate the memory bottleneck. The main idea is to use program transformation tools (also called compilers) to restructure programs so that they can best utilize deep and complex memory hierarchies, and to account for such hardware optimizations as prefetching and shared caches. This project investigates novel programming models and constructs for scalable multicore processors, and compiler techniques to support such models and constructs. It also aims to develop a runtime infrastructure for message passing aggregates to support such models and constructs on clusters of multicore processors. Software developments are augmented by analytical models that guide application development and compiler optimizations. Software techniques and theoretical models are validated for performance and scalability on platforms ranging from multicore desktop machines to clusters of multicore processors.