CSR-PSCE, SM: Operating System-Level Resource Management in the Multi-Core Era

University Of Rochester, Rochester NY

Investigators

Abstract

Multi-core processors require increasingly sophisticated operating systems and middleware in order to ensure both security and performance isolation. Operating systems need to be aware of the on-chip resource requirements of individual threads and processes. Shared resources such as parts of the memory hierarchy and the off-chip bandwidth imply that interactions among concurrently executing processes might affect their performance and perceived priority. Resource-aware policies are imperative for improved performance, fairness, and scalability. Some of the challenges faced in making the policies resource-aware include: identifying application resource requirements in a transparent manner, understanding the interactions among conflicting resource requirements, and enforcing the resource constraints in a manner that scales as the number of cores is increased. This research addresses these challenges by developing new system-level support for resource management in multi-core processors. The key idea is to use low-overhead hardware-provided statistics via counters as a mechanism to learn about resource requirements and conflicts without application involvement. Hardware counter statistics can also serve as a signature of program execution, benefiting tasks such as workload classification and phase change identification. At the level of the operating system, the project utilizes the online processor execution statistics to improve the efficiency and fairness of CPU scheduling and memory management, and manage the hardware-provided statistics as a first-class resource so that multiple applications can take advantage of the information. By working with an existing open-source OS (Linux) and virtual machine monitor (Xen), the experimental work directly impacts today's multi-core users. Strong on-going collaborations with industry partners, in particular, IBM and Ask.com, permit this team to transfer technological advancements to mainstream processors and commercial applications. As one possible outcome, the hardware design of processor counters can be augmented to cooperate with the software system support. With a better understanding of software needs (for both statistics utilization and management), more informed tradeoffs can be made at the hardware level. The education component of this project will include direct research participation of both graduate and undergraduate students as well as curriculum enhancement for related systems courses. As a result, students will acquire valuable multidisciplinary (software/hardware) experience and training required to understand and advance increasingly complex future computer systems.