CSR-PSCE, SM: Automatic Multithreaded and Transactional Memory Workload Synthesis for Efficient Multi-core Design Space Evaluation

University Of Florida, Gainesville FL

Investigators

Abstract

Multi-core systems have become mainstream in everything from server to embedded computing markets. As hardware and software designers adopt transactional memory as a cost-effective multi-core programming paradigm, evaluating TM/multi-core design, using a wide spectrum of transactional applications, is crucial to quantify the trade-offs among different design criteria. One roadblock that the TM/multi-core research and design community faces is the lack of representative transactional memory benchmarks. This project aims to develop innovative techniques, methods, and new tools for accurate, effective, and automatic transactional memory workload synthesis to address these challenges. This may be significantly beneficial to the multi-core architecture research and design community. The synthetic TM benchmarks preserve the behavior of original multithreaded workloads while the parameterized transaction synthesizer can produce transactional code with widely varied behavior that can effectively stress the TM design in different dimensions. Moreover, the parameterized synthetic workloads will have significantly reduced runtime, which allows architects and designers to quickly explore the large TM/multi-core co-design space within which numerous design tradeoffs need to be evaluated. The successful development of innovative transactional memory workload synthesis techniques, methods and tools will have significant impact on the design, evaluation and optimization of future multi-core based systems. Specifically, it will: (1) significantly improve multi-core processor and system design and research productivity; and (2) largely ensure that the design is really beneficial to multi-core oriented applications. This project's integrated education and outreach plan will help to educate a broad spectrum of citizens and students. This includes expanding computer architecture curriculum with advanced modeling and evaluation methods, recruiting minorities and undergraduate students into research, and collaborating with the computing industry to integrate the developed technologies into real-world multi-core processor design flow.