A New Approach to Design-for-Testability (DFT) Using Ultra Wideband and Wireless Communication Techniques

Virginia Polytechnic Institute And State University, Blacksburg VA

Investigators

Abstract

Proposal No.: 811706 PI: Ha, Dong S. Title: A New Approach to Design-for-Testability (DFT) Using Ultra Wideband and Wireless Communication Techniques Institution: Virginia Polytechnic Institute and State University ABSTRACT A power distribution network in an IC is ubiquitous as seen by the internal logic, i.e., a power line is accessible to any internal node. This suggests the possibility of monitoring or controlling the logic value of any internal node through a power line by attaching a simple and nearly all-digital sensing/control circuit to the node. In other words, power line communications (PLC) in an IC provides designers with an inexpensive means to access to internal nodes, which can be useful for various applications, including test application time reduction for scan design, system debugging, fault diagnosis, monitoring transient logic values during built-in self test, and on-line testing. The research investigates the feasibility and practicality of PLC in ICs with circuit testing as the major target application. Upon successful execution of the project, the major technical accomplishments are as follows. (1) it suggests a new approach to address VLSI testing problems; (2) it investigates a new area, PLC at the IC level; and (3) it develops the necessary building blocks for PLC at the IC level. The use of power lines at the IC level has not been explored before, and it offers vast new applications in VLSI testing and other areas such as intra-/inter- chip level communications. The outcomes of this research will be published in journals and proceedings and will be presented at technical conferences. The proposed research will also foster the integration of research and education and will be used to enhance the curriculum at the PI?s institution. This project provides an excellent opportunity to train undergraduate and underrepresented students in various electrical engineering fields, including VLSI testing, analog and mixed signal design, RFIC design, and circuit and system level simulation. An initial feasibility study for the proposed research has been conducted in close collaboration with a major US semiconductor company, and several other US semiconductor companies also have committed to collaborate in the proposed research. Close collaboration with those companies will provide a direct path to commercialization of the research at the successful conclusion of the project.