CPA-DA-T: Design and Tools for Easy-to-Program Massively Parallel On-Chip Systems: Deriving Scalability through Asynchrony

Columbia University, New York NY

Investigators

Abstract

Abstract NSF Proposal #0811504, CPA-DA-T: ?Design and Tools for Easy-to-Program Massively Parallel On-Chip Systems: Deriving Scalability Through Asynchrony? PI: Prof. S. Nowick (Columbia University), co-PI: Prof. U. Vishkin (U. of Maryland) Contact: Steven Nowick (Columbia University) ? nowick@cs.columbia.edu June 30, 2008 While the current reality is that the jury is still out on how the processor-of-the-future will look, one clear certainty is that it will be parallel. All major commercial processor vendors are now committed to increasing the number of processors (i.e. ?cores?) that fit on a single chip. However, there are major obstacles of power consumption, performance and scalability in existing synchronous design methodologies. This proposal focuses on a particular existing easy-to-program and easy-to-teach multi-core architecture. It then identifies the interconnection network, connecting multiples cores and memories, as the critical bottleneck to achieving lower overall power consumption. The target is to substantially improve the power, robustness and scalability of the system by designing and fabricating a high-speed asynchronous communication mesh. The resulting parallel architecture will be globally-asynchronous locally-synchronous (i.e. GALS-style), that gracefully accommodates synchronous cores and memories operating at arbitrary unrelated clock rates, while providing robustness to timing variability and support for ?plug-and-play? (i.e. scalable) system design. Unlike most prior GALS architectures, this one will have significant performance and power requirements in a complex pipelined topology. In addition, computer-aided design (i.e. CAD) tools will be developed to support the design of this new mesh, as well as simulation, timing verification and performance analysis tools to be applied to the entire parallel architecture. This work will be performed in collaboration with a separate NSF CPA proposal under Prof. Ken Stevens (University of Utah). The two proposals will be linked together into a larger framework: the Utah group will coordinate to provide and refine their commercial-based physical design tool development and support, while the Columbia/Maryland group will provide a new substantial test case for their asynchronous tool applications. The work is expected to have broad impact. First, while it is targeted to one parallel architecture, several other architectures will benefit from this work, since the interconnection network can be applied to them as well. Second, the work is expected to demonstrate the benefits and role of asynchronous design for complex high-performance systems. Finally, the outcome of the work could make a step in the paradigm shift from serial to parallel that the field is now undergoing; the resulting first-of-its-kind partly-asynchronous high-end massively-parallel on-chip computer could push the level of scalability beyond what it currently possible and have a broad impact in supporting parallel applications in much of computer science and engineering.