Parallel-on-Demand --- A Broad Purpose 3D-Integrated Performance Acceleration Layer for General Purpose Processors

Georgia Tech Research Corporation, Atlanta GA

Investigators

Abstract

With the continuing trend of shrinking feature size and advances in process technology, it would be feasible to integrate 10 to 100 billion transistors on a chip in near future. Nevertheless, one fundamental physical limit, power consumption, must be addressed to enable such trend. Power is no longer a desirable feature but an actual design constraint in making future many-core processor systems practical. On the other hand, emerging process technologies such as 3D die stacking enables a new dimension of integration and provides new opportunities for improving bandwidth, latency, and power. Given such design constraints and new opportunities, the current symmetric, homogeneous multi-core processors integrated in a MIMD manner will be inappropriate as a scalable solution from power- and area-efficiency standpoints despite their reduced implementation effort. In particular, for applications with inherently high data-level parallelism, it is possible to design new architectures that exploit the 3D stacking. In this research, a new many-core architecture, called Parallel-On-Demand (POD), will be investigated to exploit the maximum performance for a given die area and energy budget. Instead of using conventional, special-purpose ASIC accelerators, POD integrates a performance acceleration layer (PAL), which is tightly coupled as a separate die layer using 3D die stacking. PAL leverages many ideas learned from massively parallel processors but focuses on modern multi-faceted challenges such as power and area efficiency, on-chip wire delay issues, on-chip interconnects, integration with out-of-order cores, backward/forward compatibility, virtualized resource mapping, and extensibility. A 3D-integrated performance acceleration layer applied as a snap-on feature also makes the entire system flexible, reducing non-recurring engineering cost for different target markets. Moreover, new programming models will be investigated to simplify the interaction between programmers and POD, overall hardware complexity and its ensuing power implications. The success of such 3D on-die many-core architecture will provide a foundation to enable highly scalable computation with substantial energy efficiency, paving the road to Peta-FLOPS computing with minimal resources.