Design of Energy-Efficient Programmable Signal Processing Accelerators in 3D Integrated Heterogeneous Multi-Core Processor for Mobile Multimedia Communication

Rensselaer Polytechnic Institute, Troy NY

Investigators

Abstract

The objective of this research is to develop energy-efficient programmable signal processing accelerators for heterogeneous multi-core mobile multimedia communication processors utilizing three-dimensional (3D) integration technology. The approach is to use the massive storage capacity and extremely high logic-memory data bandwidth enabled by 3D logic-memory integration, realized by vertically stacking high-performance logic die and high-density memory dies together, to fully exploit the parallelism inherent in most signal processing functions. The intellectual merit lies in the research theme of jointly considering signal processing algorithm, programmable accelerator architecture, and memory modeling and optimization to most effectively exploit the unique features, i.e., storage capacity and bandwidth, provided by 3D logic-memory integration. Within the proposed scope, this research addresses video coding and forward error correction coding systems, which dominate the energy consumption of mobile multimedia communication signal processing. Because of the high storage density of dynamic random access memory (DRAM), this research will focus on 3D logic-DRAM integration and develop accurate 3D DRAM modeling and performance prediction capability in a truly technology-aware manner. The broader impacts of the research include the potential to greatly improve the energy efficiency of future mobile multimedia communication devices by providing energy-efficient programmable signal processing accelerator design solutions. In addition, the research represents a first step towards establishing a new area of 3D very large-scale integration (VLSI) signal processing that naturally expands the traditional VLSI signal processing area. The project also promotes the education of a wide spectrum of students in advances in future nanoscale integrated circuits and 3D integration.