CPA-DA: Dealing with Voltage Variations and Supply Noise During Performance Verification in Nanometer Tehcnology Designs

University Of Connecticut, Storrs CT

Investigators

Abstract

Proposal ID: 0811632, PI Name: Mohammad Tehranipoor, PI Institution: University of Connecticut, Title: CPA-DA: Dealing with Voltage Variations and Supply Noise During Performance Verification in Nanometer Technology Designs ABSTRACT: Power supply noise (PSN) will be a serious issue in nanometer technology designs especially during post-silicon performance verification and speed binning. Such effect must be efficiently taken into consideration, as it poses design, test and reliability challenges for the chip manufacturers/foundries. This situation has grown more complicated with reducing supply voltage and the limitation of further reduction of threshold voltage leading to reduced noise margin and increased circuit sensitivity. This project addresses the necessity of new comprehensive and efficient PSN analysis, power model, pattern generation, and design for testability (DFT) methods to alleviate the above issues during performance verification and speed binning in new technology generations. This project will also address the practical issues of power analysis and proposes new power model, statistical PSN analysis, and efficient measurement procedure for measuring performance degradation due to excessive voltage, process and environmental variations. The Intellectual Merit of the research is that it will significantly increase the quality and reliability of chips and reduce the manufacturing costs. The broader impact is (i) the contribution to debugging and diagnostic groups of EDA and semiconductor industry to assess and verify the performance of design prototypes, (ii) the education of undergraduate and graduate students, and (iii) the development of new courses, and (iv) the dissemination of data and methodologies to researchers in academia and industry.