SGER: Exploring the Potential for Software-Informed Hardware Reconfigurability in the Memory Hierarchy of Embedded Systems

Cuny City College, New York NY

Investigators

Abstract

Significant performance gains can be obtained when software (i.e., compiled code) is optimized to exploit the hardware (i.e., processor microarchitecture) on which it is executed. For the compiler to generate optimized code for structures such as the cache memory, it needs to know the specification of the cache hierarchy, such as the associativity, block size, and so on. In this case, the code will be optimized only for that particular cache hierarchy and is not guaranteed to perform well on other machines with different cache architectures, raising portability issues. That is, the software may not execute efficiently on a wide range of machines when optimized for only a particular architecture. In this proposal, the PI proposes a framework that enables compiled code for embedded applications to be optimized for specific cache hierarchies without suffering from portability issues. The main goal is to close the gap between compilers and processor microarchitecture by providing a virtual cache system. With this, compilers can generate optimized code for specific cache architectures. When the code is executed on machines with different cache memories, the hardware will be dynamically reconfigured to take on the characteristics of the targeted cache architecture, thus exploiting the original optimizations made by the compiler.