Low Temperature Plasma Etching of Copper to Minimize Size Effects in Sub-100 nm Features

Georgia Tech Research Corporation, Atlanta GA

Investigators

Abstract

CBET-0755607 Hess The increased complexity of integrated circuits (ICs) has yielded progressively enhanced capabilities, performance and reliability, while the IC cost per function has dropped continuously. These accomplishments have placed severe requirements on the density of interconnects used to connect the millions of transistors manufactured simultaneously. In order to meet the speed requirements for current and future generations of ICs, copper (Cu) has virtually replaced aluminum as the interconnect material. Because of an inability to develop an effective subtractive plasma-based etch process for Cu at temperatures below 180oC, damascene technology is used to pattern Cu films. Here, subtractive etching of Cu is avoided by electroplating Cu into plasma-etched dielectric trenches. Chemical mechanical planarization (CMP) is then used to remove the Cu overcoated above the trenches and dielectric, thereby creating Cu patterns. Unfortunately, the electrical resistivity of electroplated Cu increases rapidly as lateral dimensions are reduced below 100 nm; this "size effect" in electrical resistivity is a critical limitation to future device generations in the IC industry since it reduces circuit speed and can have an adverse effect on the reliability of local interconnects. In addition, control of the CMP process as well as its environmental and economic impact, are problematic. Intellectual Merit: The intellectual merit of the project involves the development of a novel low temperature Cu etch process that will facilitate improved Cu interconnect designs with higher efficiencies, enhanced speed and reduced power consumption. Thermodynamic analyses have suggested that Cu might be etched by using a two-step process: plasma chlorination of Cu surfaces followed by formation and desorption of Cu3Cl3 using a H2 plasma. Preliminary results have demonstrated the ability to etch Cu below room temperature using this approach and thus suggest that a process to plasma etch/pattern Cu films at low temperatures is possible. This research will allow the IC industry to overcome a major problem and limitation impeding the advance of semiconductor technology. This work will develop a fundamental understanding of the proposed two-step plasma process for Cu patterning and will perform preliminary pattern definition studies to evaluate the ability to anisotropically etch patterns and thus assess the potential for large scale IC manufacture. The project is ideal for chemical engineering graduate students in that experimental studies are combined with fundamental thermodynamics and kinetics investigations to address a critical industrial problem. Broader Impact The broader impacts of the project include: (1) mitigate size effects in Cu interconnects thereby removing a limitation currently existing for the advancement of IC technology, (2) develop a more environmentally benign, lower cost, effective method of patterning Cu films, (3) provide molecular level information regarding the controlling steps in low temperature etching of Cu, (4) develop novel examples and case studies for undergraduate and graduate ChBE courses, (5) educate/train minority undergraduate and high school students each summer who participate in the Georgia Tech Summer Undergraduate Research in Engineering (SURE) Program at Georgia Tech, (6) educate high school students and teachers in IC fabrication and environmental issues through the National Nanotechnology Infrastructure Network (NNIN) site at Georgia Tech and through the PI?s personal contacts in local high schools.