CAREER: Understanding and Exploring Performance-Correctness Explicitly Decoupled Architecture

University Of Rochester, Rochester NY

Investigators

Abstract

As processor microarchitecture has evolved over the past 30 years, both the complexity of the design and the number of transistors used in its realization have escalated. This complexity makes guaranteeing correct operation under all corner cases (logical as well as electrical) an ever more challenging task. This, in turn, translates in to higher and higher practical barriers for microarchitectural innovation for performance optimization as correctness is an overriding consideration. The goal of this CAREER proposal is to explore a new design model called Performance-correctness Explicitly-decoupled Architecture. From ground up, an explicitly-decoupled architecture is designed such that performance optimization circuitry is an independent entity separate from the circuitry guaranteeing functionality and correctness. This explicit separation allows performance optimization to be truly considered in a common-case-only manner, allowing the use of probabilistic techniques considered impractical or even incorrect in a conventional monolithic microarchitecture. This project seeks to develop insights to better understand this design model and develop complexity-effective microarchitectural and software mechanisms for performance optimization.