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Towards A Theory of Communication With Sloppy Analog-to-Digital Conversion: A Framework for Low-Cost Gigabit wireless

$300,000FY2007CSENSF

University Of California-Santa Barbara, Santa Barbara CA

Investigators

Abstract

The economies of scale of cellular and WiFi networks are enabled by low-cost integrated circuit implementations of sophisticated digital signal processing (DSP) algorithms in wireless communication transceivers. An implicit assumption in this approach is that analog received signals can be converted to a reasonably faithful digital representation, an assumption that breaks down as link speeds increase to the point that high-precision analog-to-digital conversion (ADC) becomes too costly and power-hungry. This project involves the design of wireless networks in the latter regime: the goal is to design low-cost links operating at multiGigabit speeds (i.e., more than an order of magnitude faster than WiFi), exploiting large swaths of unlicensed spectrum in the 3-10 GHz band and the 60 GHz band. The research rethinks communication transceiver design, with the starting assumption that high-speed ADCs are ``sloppy.'' The research involves obtaining fundamental performance benchmarks using information theory, and devising DSP algorithms that achieve these performance benchmarks. The ultimate objective is to enable a quantum leap in the speed of wireless networks for the home and enterprise, while preserving the economies of scale associated with low-cost silicon implementations. While conventional systems use 6-12 bits of ADC precision, this research considers the design of communication systems for low-resolution (1-4 bits) ADC, including Shannon theoretic benchmarks and algorithms for synchronization and equalization. Since high-speed digital-to-analog conversion is easier than ADC, precoding strategies which move complexity to the transmitter are investigated. The use of time-interleaved ADCs to attain higher precision, and hence higher dynamic range, is considered for both singlecarrier and multicarrier systems. The approach is to design receiver algorithms that jointly address mismatch between the component ADCs and the channel dispersion.

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