SGER: A Virtual Target For Next Generation Hardware Accelerated Multi-Core Systems

University Of California-Irvine, Irvine CA

Investigators

Abstract

For years, microprocessor vendors have supplied processors with increasingly faster clock speeds, ensuring the continued growth in the number of embedded products on the market. These embedded products have had a profound impact on the quality of life. Today, and as a result of physical design challenges, the industry finds itself at a turning point, with a shift of emphasis from single-processor core to multi-core systems using Field Programmable Gate Arrays (FPGAs) as means to accelerate compute-bound applications. To obtain desired performance from these new compute platforms, designers are following platform-specific programming and compilation practices. These practices yield non-portable code, and violate the principle of clean separation of function from architecture, reducing the degree of interoperability among developers, tool vendors, and architecture providers. The planned research of virtualizing a multi-core system augmented with FPGA fabric, akin to the concept of virtual machines such as Java VM, provides an abstract and universal underpinning for design and verification of complex embedded software. The research aims to explore and define a parametric virtualization layer providing an abstract view of hardware to the software subsystem and study technologies for configuration checkpointing/rollback and source level debugging support. A virtual platform will enhance and enable research in distributed software, operating systems, compilers, on-chip synthesis, device configuration, debugging, active power management, and FPGA/microprocessor design. It will serve as an important tool in the lecture room and in the hands of students, allowing them to explore, define, and refine the design paradigms of the future.