Architectural Support for Parallelism on Multi-Core Architectures

University Of California-San Diego, La Jolla CA

Investigators

Abstract

Industry is shifting from uniprocessor-oriented processors to architectures which execute multiple threads on a single chip. This includes multithreaded and, increasingly, multiple-core processors. That is, increases in transistor count and density are no longer being applied to increased single-cpu or single-thread performance. Instead, those transistors are being used to increase the number of available execution contexts. The most significant impact of this technology shift is that microprocessors will only continue to scale in performance in the presence of abundant thread level parallelism. For many workloads, the parallelism available will quickly fall short of the parallelism the hardware is able to exploit. The performance advances of future processor generations then become unavailable in those environments. This parallelism gap is inevitable, because there is no clear limit in sight to how many contexts we can place on a chip. This research will create a toolchest of solutions to enable the effective use of on-chip parallelism to improve performance, power efficiency, and correctness of programs. Particular emphasis is on applications for which traditional methods of parallelism have been ineffective. This research will focus on solutions in the following areas. More efficient parallel architectures enable better exploitation of available parallelism by ensuring that what does run in parallel does so as effectively as possible. Non-traditional forms of parallelism allow multiple contexts to provide speedup, without necessarily departing from the single execution stream model. Dynamically-generated parallelism will use lightweight hardware monitors to identify code that is potentially memory-independent, and separate threads will analyze and possibly rewrite the code to exploit the parallelism dynamically. In addition to providing performance, multi-core architectures can be exploited to provide new functionality that either is not possible, or not performance-effective, on a single core. This functionality includes software fault tolerance, debugging, and security.