NSF CCF-CPA: Reliability in the Face of Variability under Nanoscale Technology Scaling

Harvard University, Cambridge MA

Investigators

Abstract

Technology scaling has enabled tremendous growth in the integrated circuits (IC) industry over the past few decades. While Moore's Law seems to be going strong, fine line widths in current and future nanoscale technologies (e.g., 45nm and below) present several obstacles that have the potential to limit continued device scaling, curtail frequency improvements, and cause increased leakage power in future microprocessors. To make matters worse, voltage and temperature fluctuations arise from increasing power dissipation and techniques that attempt to reduce power. The combined impact of these variations forces designers to incorporate larger amounts of design margins in order to guarantee reliable operation. This proposal seeks to address the issue of variability in a cooperative fashion at both the circuit and architecture levels to ensure reliable operation of next-generation computing systems. This proposal outlines work along three main research thrusts. The first thrust investigates circuit and architectural solutions to deal with the growing concern over reliability of on-chip memories and obtaining consistent levels of performance for each manufactured chip. These concerns arise from variations when manufacturing transistors in aggressively-scaled technologies. The second thrust seeks to minimize the aforementioned margins in critical parts of a chip via flexible circuit and architecture configurations that can accommodate variations. The third thrust leverages the first two efforts to understand the impact of variability and to offer guidelines for variability-tolerant chip-multiprocessor designs.