Program Analysis for Concurrency

Stanford University, Stanford CA

Investigators

Abstract

0702681 Program Analysis for Concurrency Alex Aiken A revolution is taking place in hardware, with commodity, parallel multi-core chips replacing the sequential single-core chips that have been the dominant hardware platform for decades. Quad-core chips are now available, and chips with many times that number of cores are in the planning stages. Clock speeds are not likely to increase quickly in the future, and thus future performance gains will come primarily from exploiting the concurrency available in multi-core architectures. However, it is well-understood that our software infrastructure is not ready for this revolution, because concurrent programming remains much more difficult than sequential programming. In practice one of the biggest differences with sequential programming and a source of many serious problems is concurrency bugs. Concurrent programs today are riddled with race conditions and deadlocks. This project seeks to develop techniques that will answer the questions: Can realistic programs be automatically analyzed to accurately determine whether there are race conditions? Can the same thing be done for deadlocks? And can both problems be solved simultaneously, guaranteeing developers that their programs are free of these low-level concurrency errors?