Collaborative Research: Designing Next Generation Communication and I/O Subsystems with Multi-Core Architecture

University Of Chicago, Chicago IL

Investigators

Abstract

Multicore architectures are gaining popularity for designing next generation high-end computing (HEC) systems. Typical HEC systems with multicore processors are leading to three-levels of communication and data sharing: within the chip-level multiprocessor (intra-CMP), across chip-level multiprocessors (inter-CMP) and across different physical systems (inter-node). This leads to a fundamental challenge of how the communication and I/O subsystems of next generation HEC systems can be designed by taking advantage of these emerging multi-core architectural features. In this context, this research proposes investigation of issues in designing the following components for next generation HEC systems: (i) Multicore-aware Message Passing Interface (MPI), (ii) Enhanced MPI with dedicated communication threads, (iii) Multicore-aware I/O subsystem and (iv) Reliability and Fault tolerance. A comprehensive research plan using multiple design strategies, analytical modeling and experimental evaluation is proposed. Results derived from this research are planned to be incorporated into MVAPICH/MVAPICH2, open-source MPI packages over high performance networks.