CAREER: Hardware/Software Support for Probabilistic Architectures

Northwestern University, Evanston IL

Investigators

Abstract

This research project investigates models and methodologies for designing and managing multi-core processor resources under the extreme manufacturing variations and in-field hard failures projected for near future technology generations. These phenomena are governed by laws of probability and can be appropriately handled by methods that address the underlying uncertainty. Synergistic hardware and system software elements play a central role in achieving these goals through design forecasting, resource provisioning, self-discovery, and autonomic management. Hardware will be designed to support adaptation and in-field monitoring. System software will read in situ sensors, apply statistical inference, and use on-line learning strategies to build run-time knowledge about on-chip resources. This knowledge will be used to tune the processor for performance, power, and reliability. Manufacturing variation and operational stress will make it increasingly difficult to benefit from raw technology scaling and will potentially limit the commercial and societal impact of computing in the billion transistor era. This research addresses these challenges by enabling the design and management of efficient, reliable, multi-core processors. This project will have educational impact through research training of graduate students and incorporation of research findings into existing undergraduate and graduate courses. Members of underrepresented groups will benefit from mentoring efforts and will be active participants in research.